What question did this study set out to answer?

The aim is to develop a compact neural network for accurately reading multiplexed superconducting qubits with low latency.

February 11, 2026Open Access

Hardware-Efficient Neural Networks for Low-Latency Multiplexed Superconducting Qubit Readout

Key Points

The aim is to develop a compact neural network for accurately reading multiplexed superconducting qubits with low latency.
Utilized a lightweight neural network designed through knowledge distillation
Evaluated readout fidelity of the new model against resource-intensive alternatives
Implemented the model on Xilinx FPGA for real-time performance
Achieved a 99% reduction in model size compared to existing methods
Maintained comparable readout fidelity despite reduction in size
Attained a readout latency of only 32 ns

Abstract

Machine learning has emerged as a promising approach for the accurate state discrimination of multiplexed superconducting qubits. However, existing methods often rely on large, resource-intensive models, posing challenges for efficient hardware deployment. In this work, we present a lightweight neural network optimized via knowledge distillation, achieving a 99% reduction in model size while maintaining comparable readout fidelity. Furthermore, we implement the proposed approach on a Xilinx FPGA, achieving a readout latency of only 32 ns

Hardware-Efficient Neural Networks for Low-Latency Multiplexed Superconducting Qubit Readout

Key Points

Abstract

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