Hardware-Efficient Neural Networks for Low-Latency Multiplexed Superconducting Qubit Readout

Machine learning has emerged as a promising approach for the accurate state discrimination of multiplexed superconducting qubits. However, existing methods often rely on large, resource-intensive models, posing challenges for efficient hardware deployment. In this work, we present a lightweight neural network optimized via knowledge distillation, achieving a 99% reduction in model size while maintaining comparable readout fidelity. Furthermore, we implement the proposed approach on a Xilinx FPGA, achieving a readout latency of only 32 ns