Mask optimization in lithography is becoming increasingly important as the technology node size shrinks down. Inverse Lithography Technology (ILT) remains one of the most robust and high-performance solutions adopted in industry, yet it suffers from significant computational overhead and complexity. With the growing scale of transistor integration, industry attention has shifted toward improving efficiency and workload scalability. However, most recent academic efforts remain confined to localized pattern restoration regardless of full-chip manufacturing conditions. In this work, we present FuILT-S , a practical full-chip ILT-based mask optimization framework that incorporates sub-resolution assist features (SRAFs) co-optimization to address real-world manufacturing challenges. To enable full-chip scalability, we build a multi-level partitioning strategy following the divide-and-conquer mindset, paired with a workload distribution framework for efficient multi-GPU parallelization. To fix inter-region boundary stitching artifacts, we propose a gradient-fusion technique alongside a multi-level healing strategy. Furthermore, by leveraging rich information from the fused gradient and mask intensity maps, we integrate an SRAF generation module co-optimized with the main layout patterns. Experimental results across different layers from real-world designs demonstrate that FuILT-S is both effective and generalizable. Our framework is open-sourced at https://github.com/OpenOPC/OpenFuILT.
Yin et al. (Sat,) studied this question.
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