August 30, 2005

A 25Gb/s PAM4 transmitter in 90nm CMOS SOI

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Abstract

A 25 Gb/s multi-level PAM4 transmitter intended for short-range chip-to-chip on-board interconnects is presented. A 4-tap FIR pre-emphasis filtering scheme is used to equalize channel loss and to improve eye opening. Fabricated in a low-k partially depleted 90 nm SOI technology, it occupies 0.052 mm/sup 2/ and draws 99.3 mA from a 1 V supply.

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Menolfi et al. (Tue,) studied this question.

synapsesocial.com/papers/6a1d7975266863fda62f5656 https://doi.org/https://doi.org/10.1109/isscc.2005.1493874

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