Generation process of hole traps thermally induced in SiO2/GaOx/p-GaN metal-oxide-semiconductor structures

The impact of post-deposition annealing (PDA) and a gallium oxide (GaOx) interlayer on the generation of fast-response hole traps, which cause surface potential pinning, in SiO2/p-GaN MOS structures was systematically investigated. With a GaOx interlayer of a certain thickness formed during SiO2 deposition, the density of hole traps strongly depended on the annealing temperature but was almost independent of the annealing duration. When thermal oxidation was performed before SiO2 deposition, the hole trap density increased with oxidation time under an identical PDA condition. As a result, the PDA temperature and the GaOx interlayer thickness were found to be critical factors in the generation of hole traps: the hole trap density was about 2×1012cm−2 by suppressing the formation of a GaOx interlayer and/or lowering the PDA temperature (<300°C), while it reached about 1×1013cm−2 when these parameters were not controlled.