Defect Engineering toward High‐Performance Tin‐Based Perovskite Field‐Effect Transistors

Abstract Tin (Sn)‐based perovskite field‐effect transistors (FETs) have garnered considerable attention as promising candidates for next‐generation electronics and optoelectronics due to their exceptional charge transport properties, cost‐effectiveness, and eco‐friendly nature. However, owing to facile Sn vacancy formation, serious oxidation as well as uncontrollable crystallization, Sn‐based perovskites generally suffer from inferior film quality with high‐density defects, resulting in unfavorable self‐doping effects with high hole concentrations. Furthermore, defects within the relatively thin films (tens of nanometers) of these FETs, primarily located at the surface and grain boundaries (GBs) of perovskite films, significantly impact the charge transport, ion migration, and structural stability during device operation, thereby impeding the achievement of high‐performance Sn‐based perovskite FETs. Herein, a comprehensive overview of defect properties, origins, and their influence on the performance of Sn‐based perovskite FETs is present. In particular, the advanced defect passivation strategies, including compositional engineering, dopant modification, dimensional engineering, interface passivation, and crystallization regulation are summarized systematically. Lastly, the existing challenges and potential future prospects regarding defect engineering are proposed to achieve high‐performance Sn‐based perovskite FETs, which will pave the way for further large‐scale integration applications.