Hardware Acceleration of the LESS Canonical Form Computation

Abstract LESS is a round 2 candidate of the onramp digital signature competition currently being organized by NIST. Recent work related to LESS introduced the notion of canonical forms, which enable substantially reduced signature sizes at the cost of additional computation during signing and verification. This paper investigates a high-performance implementation of this new canonical form computation. We introduce a hardware architecture for computing the canonical form used in LESS, providing insight into the cost of this operation in hardware and the impact on the overall performance of the signature scheme.