Quantum-transport findings report improved electron mobility in Si nanowires with clamped boundary conditions, indicating varied impacts in FET types.
Electronic transport in low-dimensional structures, such as thin bodies, nanosheets, nanoribbons and nanowires, is strongly affected by electron and phonon confinement, in addition to interface roughness. Here, we use a quantum-transport formulation based on empirical pseudopotentials and the Master equation to study the effect of the phonon boundary conditions on the electron transport in field-effect transistors (FETs) based on a small cross-section (3 × 3 cells) Si nanowire (NW) and a 10-dimer-line-wide armchair-edge graphene nanoribbon (10-aGNR). For the dispersion of the confined phonons, we employ a simple empirical model based on the folding of the bulk phonon dispersion that approximates the results of the elastic-continuum model at long wavelengths. We consider two extreme cases for their boundary conditions: clamped boundary conditions (CBCs) and free-standing (FSBCs). We find that phonon confinement affects more severely Si nanowires than graphene nanoribbons. We also find that for both 3 × 3 SiNW-FETs and 10-aGNR-FETs, CBCs result in a higher room-temperature electron mobility than FSBCs, a result consistent with what previously reported for SiNWs. On the contrary, in the off-equilibrium conditions seen in gate-all-around 3 × 3 SiNW-FETs with 7 nm gate-length, FSBCs yield a higher current than CBCs, whereas in 10-aGNR-FETs, both CBCs and FSBCs result in a similar performance.
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Cai et al. (2025) studied this question.
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