A m-RGA Scheduling Algorithm Based on High-Performance Switch System and Simulation Application

High-speed switching chips are key components of network core devices in the high-performance computing paradigm, and their scheduling algorithm performance directly influences the throughput, latency, and fairness within the system. However, traditional scheduling algorithms often encounter issues such as high implementation complexity and high communication overhead when dealing with bursty traffic. To addressing the issue of bottlenecks in high-speed switching chip scheduling, we propose a low-complexity and high-performance scheduling algorithm called m-RGA, where m represents a priority mechanism. First, by monitoring the historical service time and load level of the VOQs at the port, the priority of the VOQs is dynamically adjusted to enhance the efficient matching and fair allocation of port resources. Additionally, we prove that an algorithm achieving a 2× speedup under a constant traffic model can simultaneously guarantee throughput and latency, making this algorithm theoretically as excellent as any maximum matching algorithm. Through simulation, we demonstrate that m-RGA outperforms Highest Rank First (HRF) arbitration in terms of latency under non-uniform and bursty traffic patterns.