Abstract This paper presents a comprehensive summary of the through-silicon via (TVS) technology primarily focused on its metrology and inspection for advanced semiconductor packaging. With the rapid growth of electronics technology, the size of integrated circuits (IC) continues to decrease while the functionality of components continually enhances. A three-dimensional integrated circuit (3D IC) packaging is an essential method for improving both the integration and performance of components. 3D ICs are achieved by the TSVs. These micro-nanoscale vias enable efficient electrical connections between different layers and significantly increase the device density, being recognized as the most vital technology for high performance, miniaturization and multi-functionality of semiconductor devices. Due to the small and complicated features of TSVs, various defect modes could be observed during manufacturing and operation. These TSV defects affect the performance and reliability of the devices, further leading to a whole system failure. Therefore, an accurate and effective TSV metrology and inspection technology becomes a key factor in advanced semiconductor packaging, ensuring device performance and functionality. As the application of TSVs continues to expand, the need for fast and accurate metrology becomes increasingly important. Future trends include combining current methods with artificial intelligence (AI) to further achieve inspection automation. This paper provides a comprehensive review of the main TSV metrology methods, discusses their capabilities, advantages and limitations, and provides insight into the future TSV technology development trends.
Lu et al. (2025) studied this question.