GreyConE+: Efficient Rare-Target Test Generation for FPGA HLS Designs

High-Level Synthesis (HLS) has transformed the development of complex hardware IPs (HWIPs) by enabling abstraction and configurability through languages such as SystemC and C/C++, particularly for FPGA-based high-performance and cloud computing applications. HLS streamlines design space exploration and functional verification. It allows efficient IP synthesis across various FPGA platforms. However, it also introduces security risks, such as hidden circuitry and hardware Trojans being embedded by untrusted third-party vendors. These threats can lead to data leaks, functionality disruptions and hardware damage. The risks are particularly concerning in cloud environments with multi-tenant architectures, where multiple FPGA-based IPs operate on shared infrastructure. Detecting such threats before synthesis requires robust security validation frameworks. This work presents GreyConE+ , an advanced security testing framework for FPGA-based HLS IPs, designed to detect rare-trigger vulnerabilities that often evade conventional verification methods. By integrating selective instrumentation, greybox fuzzing, and concolic execution, GreyConE+ enhances test generation and efficiently uncovers hidden Trojans and functional anomalies. Evaluations on diverse HLS benchmarks, including SystemC and ML-based C++ designs, demonstrate higher coverage, faster Trojan detection, reduced memory overhead, and lower testing costs compared to existing techniques, reinforcing its effectiveness in securing FPGA-based HLS designs.