Abstract Recently, the global issue of energy consumption has become a critical concern for the development of artificial intelligence (AI), which demands extensive computational resources and large‐scale data processing as network architectures and system algorithms grow increasingly complex. The conventional von Neumann digital computing architecture faces inherent limitations in handling the continuously growing big data, primarily due to its sequential data processing nature in vector–matrix multiplication (VMM) and the bottlenecks between processor and memory units. To address this challenge, brain‐inspired neuromorphic computing has emerged, emulating the human nervous system, particularly through memristor crossbar array architectures. These arrays function as cumulative operation units, enabling efficient parallel data processing. This paper discusses recent progress in hardware implementations of neuromorphic computing using memristor array devices, with a focus on circuit integration and on‐chip applications of AI algorithms rather than synaptic plasticity or unit‐cell switching mechanisms. The principle of parallel VMM operations is briefly reviewed, followed by hardware‐based VMM demonstrations, including convolutional transformations, neural network perceptrons, learning rule optimization, and on‐chip operations. The review also provides perspectives on future research directions, highlighting key challenges. Thus, memristor array‐based neuromorphic computing holds significant promise for scalable, energy‐efficient, and application‐ready AI hardware.
Jang et al. (2025) studied this question.