Gate Engineering Effect in Ferroelectric Field‐Effect Transistors with Al‐Doped HfO₂ Thin Film and Amorphous Indium‐Gallium‐Zinc‐Oxide Channel

This work investigates the mechanism for the memory window (MW) suppression of the ferroelectric‐thin film transistors (FETFTs) with an amorphous indium‐gallium‐zinc ( a ‐IGZO) channel. a ‐IGZO generally has an n‐type character with a high bandgap (>3 eV) and a high density of gap states, hindering the carrier type inversion. Therefore, the negative ferroelectric (FE) bound charges at the FE layer/ a ‐IGZO interface must be compensated by the positive charges of the oxygen vacancy in the a ‐IGZO layer. In contrast, accumulated electrons can compensate for the positive FE‐bound charges. Such a bound charge compensation mechanism complicates the FETFT operation and precise understanding. Experiments and simulations confirm that feasible FE switching in the bottom‐TiN or P ++ ‐Si/Al‐doped HfO 2 / a ‐IGZO/top‐TiN structure can occur only when the countercharges in the a ‐IGZO layer compensate the positive and negative bound charges. More importantly, the Al‐doped HfO 2 / a ‐IGZO interface generally involves electron trapping, which hinders FE switching and achieving a MW for the TiN gate case. When replacing the TiN gate with the P ++ ‐Si gate, the suppressed FE polarization by the depolarization effect from the SiO 2 interface layer can mitigate electron accumulation. Consequently, the P ++ ‐Si bottom electrode (BE) is more advantageous than the TiN BE regarding a MW of FETFT.