A Radiation-Tolerant 25.6 Gbps High-Speed Transmitter in 28 nm CMOS with a tolerance of 1 Grad

This paper presents a 25.6 Gbit s −1 high-speed transmitter (HST) manufactured using 28nm CMOS technology. The HST macro-block includes an all-digital phase-locked loop (ADPLL), duty cycle corrector (DCC) circuit, data pattern generator, serializer, and a driver capable of driving the differential 100Ω line as well as a silicon photonics (SiPh) ring modulator (RM). The design adopts various radiation hardening techniques, such as triple modular redundancy (TMR), physical circuit spacing, and protection against radiation-induced leakage. The circuit achieves a total ionizing dose (TID) tolerance above 1 Grad, which aligns with the future large hadron colider (LHC) detector upgrade requirements. In this paper, the architecture of the HST based on the LC tank-based ADPLL, half-rate serializer, and the source-series-terminated (SST) output driver included in the prototype chip is described. The experimental results are reported, including general evaluation as well as the radiation characterization of the HST.