All-digital background adaptive calibration system for timing mismatch in time-interleaved ADCs

E2V's EV10AQ190A sampling chip introduces a time-interleaved ADC architecture as a means of improving the sampling rate. Still, the non-ideality of the circuitry leads to the occurrence of timing mismatch among the sub-ADCs, which seriously affects the overall performance. To address this challenge, this study proposes a temporal mismatch error calibration scheme for the EV10AQ190A chip. The scheme incorporates statistical theory for mismatch estimation and a farrow-structured fractional-delay filter optimized by the Lagrange interpolation algorithm to construct an efficient and simple blind calibration system. Experiments verify the effectiveness of the system through simulation and actual sampling. The results show that the time-interleaved ADC's Spurious-Free Dynamic Range (SFDR) is improved by an average of 17.7474dB and the Effective Number of Bits (ENOB) is increased by an average of 2.3 bits after calibration.