We present a fast generative modeling approach for resistive memories that reproduces the complex statistical properties of real-world devices. By training on extensive measurement data of an integrated 1T1R array (6000 cycles of 512 devices), an autoregressive stochastic process accurately accounts for the cross-correlations between device switching parameters, while nonlinear transformations ensure agreement with the joint cycle-to-cycle (C2C) and device-to-device (D2D) write distributions. In addition to a high-level programming version, the model is also implemented in Verilog-A to enable efficient simulation of analog circuits. This statistically comprehensive model can be used to simulate crossbar sizes with up to 1024 <tex-math notation="LaTeX">×</tex-math> 1024 devices, and benchmarks show that it achieves read/write speeds several orders of magnitude higher than a variability-aware physics-based compact model and over 10 <tex-math notation="LaTeX">×</tex-math> faster than even a simplified and deterministic compact model.
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Hennen et al. (2024) studied this question.
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