A Novel Parallel Timing Synchronization Scheme for High-Speed Receivers

We address the parallel implementation of a closed-loop symbol timing synchronizer in digital receivers. Starting from a serial timing recovery loop, we propose a low-complexity parallel architecture which, unlike parallel schemes available in the literature, employs a single numerically controlled oscillator, and is practically suitable for high-speed receivers. Numerical simulations are carried out to compare the performance of serial and parallel implementations in terms of bit error rate. Results show that the proposed architecture achieves the same performance as the serial algorithm and is robust enough to ensure good performance also with high order modulations, which are critical for modern high throughput applications.