Modeling Gate Leakage Current for p-GaN Gate HEMTs With Engineered Doping Profile

The forward bias gate leakage current and forward gate breakdown voltage are important properties of p-GaN gate high-electron-mobility transistors (HEMTs). An engineered doping profile in the p-GaN layer results in a higher gate breakdown voltage and a lower forward bias gate leakage current. The use of such a technique puts additional requirements on the compact models that are used for these p-GaN gate HEMTs. An accurate compact model is needed, which considers a change in the doping profile in the p-GaN layer of these devices. This article reviews the relationship between the gate bias and the voltage drops at the different junctions in the gate structure (i.e., at the metal/p-GaN Schottky junction and the p-GaN/AIGaN/GaN junctions) considering an engineered doping profile. This relationship is then used to model the drain-source current ( <tex-math notation="LaTeX">IDS </tex-math> ) and gate leakage current ( <tex-math notation="LaTeX">IG </tex-math> ). Three different regimes in the gate current have been considered in the model: Poole-Frenkel (PF) under low bias, thermionic emission (TE) in the medium bias range, and thermally assisted tunneling (TAT) at higher bias.