Modeling and Suppression Method of Low Order Harmonics for Three-Level Inverter With Small Capacitance Value

The discontinuous pulse width modulation (DPWM) method has been applied in three-level T-type inverter with improved LCL (ILCL) filter to increase the efficiency. Nevertheless, the DPWM method features of large neutral point (NP) ripple. Moreover, in practice, to save costs, the dc-side capacitance value is small. Therefore, the NP voltage ripple in the dc-side is large, which results in low-frequency harmonics in the output currents. In addition, the low-frequency harmonics are coupled with the ILCL filter. In this situation, the conventional low-frequency harmonics suppression methods are not applicable. To overcome these issues, a model of NP voltage ripple is established, which reveals that the NP voltage ripple results in the fifth and seventh harmonics in the output currents. Then, a proportional integral resonant (PIR) controller is introduced to suppress the fifth and seventh harmonics. However, the PIR controller will introduce new low-frequency harmonics. To solve the coupled problems, the generating mechanism of the newly appeared low-frequency harmonics is demonstrated, which is coupled with the PIR controller and the ILCL filter. Therefore, based on the generating mechanism, a notch filter is adopted to reduce the newly appeared low-frequency harmonics. Finally, the effectiveness of the proposed scheme is verified by experiments.