LOG-CIM: An Energy-Efficient Logarithmic Quantization Computing-In-Memory Processor With Exponential Parallel Data Mapping and Zero-Aware 6T Dual-WL Cell

This article introduces the logarithmic quantization computing-in-memory processor (LOG-CIM), an advanced processor that extends the capabilities of conventional linear quantization (INT) by integrating logarithmic quantization (LOGQ) into computing-in-memory (CIM) architectures. Emphasizing three key features, the LOG-CIM significantly achieves high energy efficiency and memory density using LOGQ: 1) exponential parallel data mapping (EPDM) not only facilitates efficient shifted alignment and data accumulation, optimizing the processing pipeline for LOGQ complex computations but also achieves a 51.5% improvement in energy efficiency as a result; 2) the implementation of a zero-aware dual-word-line (ZADU) cell, which not only enhances parallelism but also reduces computation power by lowering read power 88.9% for 89.3% bit sparsity; and 3) shift-addition peripheral (SAP) logic, which maximizes throughput by performing the addition of different bit positions from two data read by the ZADU cell before they enter the adder tree, thereby enhancing 24.3% energy efficiency. The LOG-CIM is fabricated in 28-nm CMOS technology and occupies a 5.832 mm 2 with a total of 48-kB on-chip CIMs. It achieves 192 TOPS/W using conventional data mapping at 4-b INT weight and 4-b input activation and 116.4 TOPS/W using EPDM at 4-b LOGQ weight and 8-b INT input activation at 120-MHz clock and 0.85-V supply voltage with the ResNet-50 @ ImageNet dataset. When using the 4-b LOGQ weight for inference, the energy efficiency was 3.54 times higher than the 8-b INT weight with similar accuracy. During training, using 4-b LOGQ weight to reach the same accuracy increases epoch compared with using only 8-b INT weight, but consequentially saves 68.7% in relative total energy. Furthermore, it achieves 599-kb/mm 2 memory density.