Electrical Characterization and Reliability Studies of Nano-TSV

Nano-TSV formation using Silicon (Si)-On- Insulator (SOI) wafer was demonstrated previously. In which, Si thickness can be precisely controlled using the proposed wafer thinning method. The developed platform is targeted for use as backside power delivery network (BS-PDN). In this work, we had designed and fabricated 180 x 500nm nano-TSV chain and leakage test structures. The Si layer is 75nm thick. In the nano-TSV, the liner and barrier/seed materials are Al <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> O <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> and Ta/Cu, respectively. Thereafter, the nano-TSV is filled by Cu eletro plating (ECP) as filling metal. Finally, the wafer frontside and backside are metallized with aluminum for electrical characterization and reliability studies. We first collected nano- TSV chain resistance and leakage electrical data directly after fabrication. These electrical tests were then repeated after subjecting the samples to reliability test conditions, including (1): Thermal Cycling (TC) (2): High Temperature Storage (HTS) and (3): uHAST. The result shows that the nano-TSV process is robust to survive through reliability stress conditions.