Test power Optimization Using Power Gating Techniques

A primary challenge in contemporary VLSI circuit design is imperative to optimize circuits for low power consumption. The escalation in device scaling worsens the issue of leakage power within the circuit. Among the available remedies, power gating stands out as a highly effective solution to mitigate standby leakage currents during idle periods. The main component employed in power gating is the sleep transistor, which is a crucial component in isolating the power supply (VDD or GND) from the standard cells in a particular design. Sleep transistors, appropriately sized as pMOS or nMOS, serve as the fundamental elements for powering down designated portions of the design. The underlying concept of power gating involves strategically disconnecting power sources from standard cells, contributing to substantial reductions in leakage currents during idle states. An approach to diminish the power consumption of specific fundamental gates, CMOS Inverter, D flip-flop, and conventional4-bit, 8-bit, 16-bit, and 32-bit linear feedback shift registers (LFSR) is implemented using conventional method, an assessmentof the leakage power is conducted employing various power gating methods. The circuits were implemented using Cadence Virtuoso Tool using gpdk180.