Device Model and Energy Loss Mechanism of Enhancement-Mode p-GaN HEMTs Under Unclamped-Inductive-Switching Stress

This article reveals the single-pulse and repetitive-pulse unclamped-inductive-switching (UIS) withstanding device model and energy loss mechanism for p-GaN high electron mobility transistor (HEMT) with Schottky type gate contact. Usually, silicon/silicon carbide (Si/SiC)-based devices dissipate the surge current from the load inductor through the avalanche process. However, p-GaN HEMT can withstand the energy by storing it in the output capacitance and dissipating it by the output capacitance loss and drain leakage current loss. The device models are proposed to describe the UIS process. The maximum current loss caused by the energy storage process of the output parasitic capacitor is about 30%. During high-voltage processes, the energy loss by leakage current is of the same order as the storing energy in the inductor, so a parallel resistor is added to the device model. The parallel resistor varies based on changes in maximum voltage and maximum current during the UIS process. The experimental results are basically consistent with the theoretical calculation results. After the repetitive UIS stresses are applied to the device, the threshold voltage shifts positively and the on-resistance increases.