Charge-based Sense Demonstration in 1T-1C HZO FeRAM Arrays to Overcome CBL-induced Bank Size Limitations

In this paper, we propose a new charge-based sensing scheme for read operation in ferroelectric random access memory (FeRAM) arrays. Experimental demonstration on 16kbit up to 256kbit Hf <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</inf> Zr <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</inf> O <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> (HZO)-based one transistor - one capacitor (1T-1C) FeRAM arrays reveals that this capacitive trans-impedance amplifier (CTIA)-based sensing has several key advantages over conventional voltage-based sense amplifiers (SA). The major benefits of this innovation are i) a median memory window (MW) as large as 1000mV which is ii) quasi-independent of array size, overcoming the well-known MW closure with bitline capacitance (C <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BL</inf> ) increase observed in FeRAM arrays with conventional voltage-based sense. This new sensing scheme is expected to be of most importance for large HZO FeRAM arrays integrated at advanced nodes, as it enables to increase memory bank size.