Gate-All-Around SRAM: Performance Investigation and Optimization Towards Vccmin Scaling

In this paper, we evaluate GAA SRAM performance and compare it to FinFET SRAM. Our modeling indicates that GAA SRAM can have better stability, writability and read-current compared to FinFET SRAM, primarily due to better electrostatics and drive-strength ratio between nMOS and pMOS. Design optimizations through varying nanosheet count and introduction of backside power delivery network allows GAA SRAM to be tailored for different applications. Furthermore, we show that, due to lower process variability, GAA SRAM can achieve lower operating voltages (Vccmin) than FinFET SRAM.