VLSI Design of Intellectual Property Design of Advanced Encryption Standard

This concise exposition posits an area-efficient method for designing AES, duly considering the distinctive implementation characteristics of FPGAs. Given that the majority of the AES hardware area is occupied by Sub-bytes and Mix Columns, this document prioritizes the optimization and evaluation of their design strategy. Centered on variations in the data path, it scrutinizes the intricate trade-off dynamics between area and clock cycles, culminating in the presentation of an area-efficient AES intellectual property (IP) design. Proposing a 128-bit AES architecture grounded in picture cryptography, this study undertakes the Verilog HDL implementation and simulation in Matlab Tool and Model Sim 6.4c. The assessment of performance employs the Synthesis Process of the Xilinx tool. The AES is a prominent data encryption specification that has evolved into one of the most extensively employed encryption systems, featuring both software and hardware implementations. It embodies a symmetric cryptography technique endowed with robust security, meticulously crafted through the use of FPGA.