Power Efficiency Evaluation of Dual Edge Triggered Flip-Flops - A Comparative Analysis

Dual Edge Triggered Flip Flop (DET FF) is a sequential circuit element that record data at both the positive and negative edges of the clock signal which results in faster throughput in contrast to Single Edge Triggered Flip Flop (SET FF). DET FF can be modelled using two different methods: Latch-MUX and C-Element. A True Single Phase Clock Static DET FF (TSPC SDET FF), a Latch-MUX DET FF which helps in solving clock overlap issue comparing to Static DET FF. On the other hand, a Floating Node C-Element DET FF (FN C-DET FF) is a C-Element type which faces issues of contention that can be taken care of by sizing the transistors. A Fully Static True Single Phase Clock DET FF (FS-TSPC DET FF) belongs to the Latch-Muxcategory which is fully static and contention free, but power consumption is high when compared with earlier designs. This research aims to provide a comparative analysis of total power consumption across three different technology nodes such as 180nm, 90nm and 45nm for various models of DET FFs mentioned above. The Schematic circuit has been implemented by Cadence Virtuoso and the simulations have been performed with Spectre simulator by Cadence.