Novel Strategies Toward High-Performance FeFET for Computing In Memory Application

Ferroelectric Field-Effect Transistors (FeFETs) attract the interest of researchers due to their capability of low power and high-speed operation for computing in memory (CIM). However, challenges with the poor memory window (MW) and reliability of FeFETs have triggered problems of density and reliability for CIM. Our study addresses these obstacles through a comprehensive approach, including materials, devices, and array architecture. We successfully demonstrated robust ferroelectric properties for relatively thick (~30 nm) ferroelectric (FE) materials. Furthermore, we adopted a metal-FE-metal-insulator-silicon (MFMIS) stack, enabling a controlling voltage distribution between FE and MIS components. This resulted in a wide MW ( <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">≥</tex> 11 V), improved switching speed ( <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$< 50$</tex> ns), and excellent endurance ( <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">≥ 10¹⁰</tex> cycles). Additionally, we demonstrated vector-matrix multiplication (VMM) operation using a fabricated FeFET-CIM array. We expect our research to offer a viable foundation for future research in CIM.