Reliability analysis and mitigation for analog computation-in-memory: from technology to application

The computation-in-memory (CiM) paradigm is widely acknowledged to tackle the memory wall problem. Additionally, leveraging non-volatile resistive memory (NVM) technologies enhances the energy efficiency of the CiM by enabling analog computation. However, the reliability of the NVM-CiM is challenged due to the inherent device and circuit imperfections, the technology-level process variation, the sensing offset, and the analog nature of the computation. In this paper, we perform comprehensive reliability analysis and mitigation from the technology all the way to the CiM application. For this aim, we accurately model the NVM device variability and imperfection and effectively model the consequent errors at the circuit level by considering crossbar parasitic and sensing offset. Subsequently, we inject these modeled faults into the CiM-enabled full-system architecture. The study quantitatively assesses the masking capability of CiM applications and explores potential mitigation techniques to enhance the overall reliability of NVM-CiM.