Innovative Practices Track: Session 2 Silent Data Corruption

For large scale data center fleets, a single Silent Data Error (SDE) event leading to computational inaccuracies has the potential to be disruptive to their end users especially when mission critical workloads are being run. With large deployments of machines in the data center, SDE rates as low as 10FIT can be detected. At the same time, silicon die area and core count in an SOC is continuing to increase with advanced packaging technologies further making it challenging. Intel has developed DCDiag tool that has a suite of diverse tests that rely on pseudo-random data and instruction combinations to detect data miscompute. These tests can be studied empirically to develop optimization methods to identify test content for effectively detecting SDEs at CPU manufacturing flow, ODM screening flow and infield fleets. While optimizing screening content is key and could be different across product generations, detecting SDEs is challenging since many of the data miscompare errors are dependent on a combination of conditions that may exist during an error. This leads to poor repeatability of DCDiag tests to capture the SDE fails which demands long test times and/or resiliency methods to minimize impact. This presentation outlines the challenges for SDE detection from CPU manufacturing to Data Center fleets and the why the notion of resilience in HW and SW is critical in data centers.