THz CMOS designs are challenging due to low supply voltages, limited transistor speeds, lossy silicon substrates, and unfriendly back end of the lines. In this talk, we will delve into the design challenges of THz electronics using CMOS technologies for both THz sensing and communication applications. We will show our efforts to address the issues mentioned above from the device-level transistor layout optimization using an electromagnetic modeling approach for enhancing fmax from 288 to 394 GHz in a 40-nm CMOS technology up to the system-level THz imaging demonstration with the spatial resolution of 1.4 mm at 336 GHz.
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Chun-Hsing Li (2024) studied this question.
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