A 20Gb/s QPSK Receiver with Mixed-Signal Carrier, Timing, and Data Recovery Using 3-bit ADCs

This is the authors' abstract. We don't add key points for this paper.

Coherent demodulation of a received signal requires the same carrier signal as the one used by the transmitter (TX). Thus, the RX needs to reconstruct the carrier from the received carrier-less signal. This is known as carrier recovery and is typically done, along with symbol timing (= clock) and data recovery, by intensive digital signal processing (DSP) following high-resolution analog-to-digital conversion (ADC). However, the ADC+DSP for a few tens of gigabits per second or faster is not easily achievable. Not surprisingly, in some ultrahigh-speed RX ICs, carrier recovery and demodulation were done not by the IC itself but by a high-end realtime oscilloscope. ADC-Iess direct-demodulation RXs reported recently [1]–[6] addressed the challenge of energy-efficient demodulation. We present a 22nm CMOS 20Gb/s QPSK RX prototype, which receives a 20GHz RF or IF signal and simultaneously performs carrier, timing, and data recovery, and outputs digital data, adopting a mixed-signal approach. It is intended to be used in a sub-THz RX at the IF. We will, therefore, refer to IF and RF interchangeably below. The strong demand for noise immunity at sub-THz makes QPSK a modulation of choice and the use of low-resolution (~3-bit) ADCs [7] a realistic possibility.