Experimental and Numerical Investigations on Amalgamation of Mixed Frequency Carrier Based Asymmetrical 15 Level Multilevel Inverter

Abstract This research encompasses the investigations of a multicarrier based 15 level multilevel inverter in an asymmetrical mode. The series connection of three voltage sources (12V, 24V and48 V) with three metal oxide semiconductor field effect transistor (MOSFET) switches and a parallel H Bridge are used to construct the multilevel inverter. The Phase Disposition configurations of triangle carrier and inverted sine carrier are selected for the investigations. The indigenous thorough Pulse-width modulation (PWM) has been generated for three series switches from the comparison of seven carriers with a reference. The two frequencies (1 kHz and 4 kHz) are chosen for carriers. The 4 kHz frequency carrier will be active only at the peak of the sine reference i.e between 5π/12 ≥ θ ≤ 7π/12 in positive half cycle and between 17π/12 ≥ θ ≤ 19π/12 in negative half cycle, remaining period 1 kHz frequency carrier has been active. These schemes have been verified with single phase MLI with RL load. The MATLAB based simulation results of fours schemes are presented. Field programmable gate array based experimental result of best scheme among four is reported and corresponding hardware results are evidenced. Xilinx Vivado design suite has been used for design synthesis and bit file generation for the FPGA.