A Novel Induced Offset Voltage Sensor for Separable Wear-Out Mechanism Characterization in a 12nm FinFET Process

Increasingly detailed predictive modelling and monitoring of semiconductor wear-out benefits greatly from on-chip measurement of transistor degradation under different voltage stress regimes. To this end, we present a novel sensor architecture leveraging direct current (DC) readout for product designs where precise timing sources are unavailable. Our design avoids wear-out in ancillary transistors and compensates for process, voltage, and temperature variations to ensure measurements track induced shifts in threshold voltage under a configurable stress regime in isolation. The proposed architecture is described in detail and a review of existing DC sensors for monitoring semiconductor degradation is included to enable comparative analysis of our design. Sensor functionality is validated via implementation in a 12nm FinFET process. Accelerated wear-out testing is conducted via a custom automated test system. Experimental results demonstrate that the design is capable of separately monitoring transistor degradation under different stress regimes and highlight observed wear-out behaviours in nanometre-scale transistors.