Adaptive Clock Gating for Improving Wear out induced Duty Cycle Shift in the Clock Network

Reliability of the clock signal is critical for the digital and analog system in the nanometer technology. Duty cycle is one of key metric in the performance of the clock signal. In this work, we explore the impact of wear out induced duty cycle shift in the clock network and propose adaptive clock gating for improving the reliability. Aging behavior of the clock network with conventional clock gating is measured with the tri-gate CMOS technology. Conventional clock gating shows asymmetric duty cycle shift due to clock gating with one polarity. This paper presents various clock gating scenarios where duty cycle behaves differently for the lifetime. The proposed adaptive clock gating approach selects the optimal polarity for clock gating by monitoring duty cycle on chip. The work demonstrates to maintain the duty cycle within the target duty cycle.