On-Chip Cross-Layer Infrastructure to Leverage System Reliability for Aero-Space Applications: Embedded Tutorial

This tutorial summarizes the on-chip infrastructure such as sensors and dedicated HW redundancy under development at IHP Microelectronics. This infrastructure deals with, for instance, detecting single-event upset (SEU) in memory elements and single-event transient (SET) in logic, measuring electronics aging and tracking in-field realtime circuit speed performance degradation during IC lifetime. Furthermore, after manufacturing process, on-chip sensors can also be used to assess silicon for device screening. Ultimately, this infrastructure allows predicting in-flight SEU rate and remaining IC life-span. Dedicated on-chip watchdogs to guarantee mixed-criticality task execution in realtime operating system (RTOS) is further introduced. Embedded systems based on such watchdogs are assumed to be compliant with the ARINC 653 Std. Currently, this on-chip infrastructure is being implemented by IHP in different versions of a RISC-V processor. Such design is based on a CMOS 130nm rad-hard technology also developed at IHP.