A 2 GHz High-Performance Design of Braun Multiplier with Hybrid Full Adder for ALU

For applications of signal processing that are both economical and computationally intensive, efficient arithmetic circuits are required. High-reliability and portable circuits are required for electronic appliances including pagers, laptops, and notebook computers. Power dissipation has grown in relevance with the introduction of high-performance chips for effective chip design. To achieve high throughput and low power dissipation, it is now more important than ever to investigate efficient design methodologies. In the past few years, high-performance VLSI design has become more and more dependent on low power and fast circuits. An Adder and a Multiplier are the basic components of an Arithmetic & Logic Unit (ALU). An adder, is an essential unit of every ALU, performs the addition function. And a multiplier is created using this adder as a foundational element. Thus, any DSP application such as FFT or others must use multiplication as a fundamental building block. Subsequently, new strategies for planning arithmetic circuits are expected to come from the results that are wanted concerning area, power, and time. The significant objective is to make a high-performance adder and Multiplier that can work at a clock recurrence of 2 GHz. Pass transistors, transmission gates, and traditional correlative metal oxide semiconductors are utilized in the design of the proposed hybrid full adder. The aforementioned adder has been used to construct the Braun multiplier architecture for multiplication operations. Additionally, it is computed how much power and propagation delay each circuit dissipates on average. And Synopsis - PrimeSim Tool was used to complete the entire design. Our proposed system Braun Multiplier with Hybrid Full Adder achieved a very significant reduction in delay, by 80%. This translates to a potential operating frequency of around 6.7 GHz.