Hardcaml: An OCaml Hardware Domain-Specific Language for Efficient and Robust Design

Hardcaml is an embedded hardware design domain specific language (DSL) implemented in the OCaml programming language. Unlike high level synthesis (HLS), Hardcaml allows for low level control of the underlying hardware for maximum productivity, while abstracting away many of the tedious aspects of traditional hardware definition languages (HDLs) such as Verilog or VHDL. The richness of OCaml's type system combined with Hardcaml's fast circuit elaboration checks reduces the chances of user-introduced bugs and erroneous connections with features like custom type defining, type-safe parameterized modules and elaboration-time bit-width inference and validation. Hardcaml tooling emphasizes fast feedback through simulation, testing, and verification. Hardcaml includes both a native OCaml cycle-accurate and event-driven simulator, along with backend support for external simulators such as Verilator. Unit tests can live in the source code, which can optionally include digital ASCII waveforms representing the simulator's output. Hardcaml also provides tools for SAT proving and formal verification. For several years Hardcaml has been industrially proven in many FPGA designs internally in Jane Street.