A 4-bit 28-GS/s 4×Time-Interleaved Current-Steering DAC for High-Speed Interfacing

In this work, a fully integrated 4-bit current-steering DAC was implemented into silicon using a 22nm SoI CMOS process node. By exploiting the time-interleaved design approach, a sampling frequency of 28-GS/s was achieved, enabling high-speed interfacing capabilities between analog and digital circuitry. The time-interleaved design approach, proposed in this work, uses an insightful current superposition technique, extending the time-interleaved factor barrier while maintaining high signal integrity and high conversion linearity, without compromising the spectral content of the output signal. For validation purposes of the proposed design approach, RLCk-aware parasitic extraction of the physical layout using Ansys RaptorX was employed and RLCk-aware simulations of the full design were performed. The performance degradation due to physical layout parasitics was compared with the schematic-view simulation scheme of the full design and it was quantified by monitoring the ENOB, SINAD and SFDR dynamic metrics of the design.