Characterization & Implementation of ISFET Array Chip Using 0.18μm CMOS Technology for Integrated Sensor Application

We implemented an ion-sensitive field effect transistor (ISFET) array chip comprising n-ISFET and p-ISFET for sensor application using 0.18[Formula: see text][Formula: see text]m CMOS technology. N-channel metal-oxide semiconductor (NMOS) and P-channel metal-oxide semiconductor (PMOS) ISFETs are fabricated in regular dimensions ([Formula: see text]8[Formula: see text][Formula: see text]m) compatible with the standard CMOS process. We implemented n-ISFET cells and p-ISFET cells of different dimensions for characterization and to observe the possible effect of scalability. Each cell also has two identical NMOS and PMOS ISFETs of standard dimension, unlike very large dimensions ([Formula: see text]200[Formula: see text][Formula: see text]m). We are using metals 1–6 and via together on the gate area to make it an extended or floating gate for the electrochemical sensing of ISFET. These metals are electrically floating with an intermediate dielectric. These different-size floating gate ISFETs provide different sensing areas, and the passivation Si 3 N 4 layer is used for pH sensing without any extra post-processing measures. We observe the ISFET sensitivity and performance with the 0.18[Formula: see text][Formula: see text]m technology submicron effect. The measured results propose ISFET as a promising sensor device for portable applications. The ISFET chip dimension is 1179[Formula: see text][Formula: see text]m × 1185[Formula: see text][Formula: see text]m.