Hardware accelerator design for object detection based on convolutional neural network

Most deep learning models for object detection are designed based on convolutional neural networks, requiring powerful computing and storage capabilities typically provided by hardware platforms such as GPUs and CPUs. In contrast, FPGAs offer low power consumption and strong computational capabilities; however, deploying neural network models directly on FPGA embedded platforms is challenging. To address these issues, this paper takes the YOLO-V3 target detection algorithm as an example, introducing the hierarchical structure of the YOLO-V3 network, analyzing acceleration methods for each layer in the YOLO-V3 network, designing a convolutional neural network accelerator, and comparing its performance with that of GPUs. The designed accelerator effectively utilizes FPGA hardware computing resources, achieving an overall average performance of 192.229 GOP/s.