Virtual FAB Semiconductor Process Modeling Augmented Vertical Gate All Around Complementary FET Based 6T SRAM Path-Finding

Vertical Gate All Around Nanowire Complementary FET based logic circuits offer an alternative way for higher cell density without aggressive gate length scaling. In this study, we develop a device to circuit design-technology co-optimization (DTCO) flow that incorporates Virtual Fab Semiconductor Process Modeling and physics-based TCAD simulations. We compare VGAA Complementary FET (CFET) based 6T SRAM with its counterparts by conventional planar CMOS, sequential/monolithic 3DIC CFETs with lateral transistors, accounting for the parasitics from virtual fab modeling. Our results show that VGAA CFETs offer better control over the channel and reduce parasitic capacitances and resistances compared to the counterpart technology options.