Logic Synthesis for XOR-AND Graphs via Reed-Muller Representations

Logic synthesis, as a key step in the design flow of modern integrated circuits, plays an important role in the development of emerging technologies and quantum computing. XOR-AND graphs (XAGs) is used to express Boolean functions that are widely used in cryptographic security application. In this paper, we propose a new rewriting approach based on the Reed-Muller (RM) logic expansion. To find an area-efficient representation of the logic network, the cuts of the logic network are enumerated and then the RM logic expansion based on mixed polarities is utilized. By conducting the experiments over EPFL benchmarks, we achieve a maximum reduction of 50% in the number of XOR gates and a normalized geometric mean of 25%.