A Compact 3–20-GHz 106-ps Passive True-Time Delay Circuit in 65-nm CMOS

This letter introduces a compact broadband true time-delay (TTD) circuit that integrates switch-based TTD and configurable artificial transmission lines (ATLs), ensuring both a wide delay range and high precision. The delay unit adopts a spiral ATL for a compact and broadband flat delay. To balance the insertion loss between reference and delay states, an attenuation unit is incorporated into the switch delay circuit. Series–parallel MOS switches are employed to mitigate resonance issues stemming from switch parasitic capacitance. The proposed TTD circuit is implemented using a 65-nm CMOS process. Measured results reveal that within the 3–20-GHz frequency range, the delay increment is 2.35 ps, with a maximum delay range of 106 ps, a group delay rms error less than 1.7 ps, an insertion loss ranging from 5.7 to 17 dB, and an insertion loss variation below ±2 dB.