An FPGA-based front-end module emulator for the High Granularity Timing Detector

This paper introduces an FPGA-based front-end module emulator developed for the High Granularity Timing Detector (HGTD) within the ATLAS experiment at LHC. The emulator serves as a debugger for the HGTD readout system during the stage when the front-end module is not available. Using a Xilinx-Spartan 7 FPGA, the emulator mimics the behavior of the ASIC utilized in the front-end module. In addition, it shares the same dimensions and connectors as its successor, the real front-end module. This emulator has been effectively employed in the design and testing of the HGTD.