Test response compression using compression perception theory

This paper presents a method for compressing test response data using compressive sensing theory to improve chip testing efficiency. The proposed approach preprocesses the test response vectors, ensuring compatibility and eliminating duplicates. These preprocessed vectors are multiplied with sparse random matrices corresponding to the tested circuit. The test response vector with the highest coefficient is selected as the compressed result by comparing the absolute values of the resulting coefficients. Experimental results demonstrate that our approach achieves superior compression ratios and fault coverage compared to other methods. Our approach improves the compression rate by nearly 15% and maintains fault coverage above 90% with less than 1.5% loss of fault information. Overall, our proposed approach offers significant advantages over existing techniques.