Dynamic Power Reduction in dual edge triggered D-Flip-flop clock gating using Memristor

This work demonstrates a dual edge-triggered D-type flip-flop with a half-static clock gating circuit based on a memristor. Half static latch is coupled in parallel with two dynamic latches, and each response is according to the gated clock's positive and negative edges. This configuration improves the circuit compactness, energy efficiency and race tolerance. Cadence virtuoso (90nm GDPK library) CMOS technology is used for simulation, and the VTEAM model is used for memristor gating implementation. In this work, the transistor count is 33. Power dissipation is 8.364μw, and clock to Q delay is 150.7 ps, less than the existing design.