Layout to SEM: hotspot prediction via SEM image synthesis

Since the rise of transistors and integrated circuits, the semiconductor industry has seen rapid advancements, leading to today's microchips containing hundreds of millions of transistors. A pressing challenge in this industry is the emergence of defects, termed "hotspots," during the manufacturing process, affecting chip performance and reliability. In this study, we introduce a deep learning model that predicts hotspots during the design stage. To predict hotspot, our proposed framework generates Scanning Electron Microscopy (SEM) images from layout by combining segmentation and image-translation network. This model outperformed existing baseline models when tested on real industrial datasets, promising to refine the semiconductor design workflow.