A 3-nm FinFET 27.6-Mbit/mm² Single-Port 6T SRAM Enabling 0.48–1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking

A 3-nm FinFET single-port (SP) 6T SRAM macro is proposed that utilizes a far-end pre-charge (FPC) circuit and weak-bit (WB) tracking circuit. These circuits can decrease write cycle time by decreasing the pre-charge period and engaging read cycle time by enhancing the trackability of sense enable timing over supply voltage. A prototype of the 434-kbit SP SRAM macro on 3-nm FinFET technology was designed and fabricated. The bit density is 27.6 Mbit/mm2 and it achieved an operation of 1.9 GHz at 0.75 V and 85 °C, which is 35% faster than conventional performance. Measured silicon data demonstrate a wide operating voltage range of 0.48–1.2 V. This proposal has also achieved the best figure of merit (FoM) compared to other works, as defined by density <tex-math notation="LaTeX">× </tex-math> access per second (APS)/supply voltage ( <tex-math notation="LaTeX">VDD </tex-math> ).