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October 16, 2025Open Access

A Novel Analog-Computing-in-Memory Architecture with Scalable Multi-Bit MAC Operations and Flexible Weight Organization for DNN Acceleration

Key Points

The novel architecture significantly enhances throughput through a pipelining scheme for operations.
Latency, energy consumption, and utilization are improved through efficient data movement reduction.
Flexible weight organization across the CIM array optimizes deep neural network performance.
Comparing this architecture with existing approaches showcases its advantages in various metrics.

Abstract

Deep neural networks (DNNs) require efficient hardware accelerators due to the high cost of vector–matrix multiplication operations. Computing-in-memory (CIM) architectures address this challenge by performing computations directly within memory arrays, reducing data movement and improving energy efficiency. This paper introduces a novel analog-domain CIM architecture that enables flexible organization of weights across both rows and columns of the CIM array. A pipelining scheme is also proposed to decouple the multiply-and-accumulate and analog-to-digital conversion operations, thereby enhancing throughput. The proposed architecture is compared with existing approaches in terms of latency, area, energy consumption, and utilization. The comparison emphasizes architectural principles while deliberately avoiding implementation-specific details.

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